Upcoming reboots during the week of October 24 will cause tool sessions to be lost. This notice will be updated with the day and time. Sorry for any inconvenience.


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Nano-Engineered Electronic Device Simulation Node

NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, U.C. Berkeley, and Stanford.

A short overview of the NEEDS initiative and several of the presentations and posters from the 2016 annual meeting are now available.
NEWEST COMPACT MODEL RELEASE:  Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETsSee Compact Models Page
NEEDS announces the public BETA testing of VALint, an automatic Verilog-A code quality checker. 
Paper "Well-Posed Models of Memristive Devices" by Tianshi Wang and Jaijeet Roychowdhury

Compact Models

Verilog-A format
supporting resources


Compact models:

Tools for devlopers including MAPP & VALint.

 VALint now in open BETA

Compact models: resources for developers                                                                                        

Seminars and tutorials for developing and publishing compact models

 Publish your compact model in NEEDS

nanoscience to systems

Physically-detailed simulations
system level tools

 Stanford script-based toolkit for system analysis

nanoscience: Seminars, Courses, etc.                                                                                                   

NEEDS Seminars, workshops, nanoHUB-U and more

 Seminar series on devices for 5 nm technology