Support

Support Options

Report a problem

Close

Compact Model Tools

Model and Algorithm Prototyping Platform (MAPP)

NEEDS has developed a platform to address the barriers to creating high-quality, physics-based compact models for emerging nanodevices. This simulation-ready, open-source, compact model development environment will be Verilog-A compliant as far as possible, but it goes beyond Verilog-A with new capabilities needed for nanodevices. It will provide a complete environment for developing, testing, experimentally validating compact models and for inserting them in commercial and open source SPICE-compatible simulation platforms.

Resources

MAPP Publications

  1. (invited paper) Tianshi Wang and Colin C. McAndrew, "A Generic Formalism to Model ESD Snapback for Robust Circuit Simulation." Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Sept 2018.
  2. A. Gokcen Mahmutoglu, Xufeng Wang and Jaijeet Roychowdhury, "New Generation Verilog-A Model Development Tools: VAPP and VALint," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2018-89, July 2018.
  3. Tianshi Wang and Jaijeet Roychowdhury, "Modelling Optical Devices and Systems in MAPP." EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2017-160, Oct 2017.
  4. (invited paper) Tianshi Wang, "Modelling Multistability and Hysteresis in ESD Clamps, Memristors and Other Devices." in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Apr 2017.
  5. Archit Gupta, Tianshi Wang, A. Gokcen Mahmutoglu and Jaijeet Roychowdhury. "STEAM: Spline-based Tables for Efficient and Accurate Device Modelling." in Proceedings of the 22nd IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2017.
  6. Tianshi Wang and Jaijeet Roychowdhury, "Well-Posed Models of Memristive Devices." arXiv preprint arXiv:1605.04897, 2016.
  7. Tianshi Wang and Jaijeet Roychowdhury, "Multiphysics Modelling and Simulation in Berkeley MAPP." IEEE International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), July 2016.
  8. A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury, "Well-Posed Device Models for Electrical Circuit Simulation." nanoHUB.org, 2016.
  9. (invited paper) Tianshi Wang, Aadithya V. Karthik, Bichen Wu, Jian Yao and Jaijeet Roychowdhury, "MAPP: The Berkeley Model and Algorithm Prototyping Platform." in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sept 2015.
  10. Tianshi Wang, Aadithya V. Karthik, Bichen Wu and Jaijeet Roychowdhury, "MAPP: A Platform for Prototyping Algorithms and Models Quickly and Easily." IEEE International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Aug 2015.
  11. Tianshi Wang and Jaijeet Roychowdhury, "Design Tools for Oscillator-based Computing Systems." in Proceedings of the 52nd Design Automation Conference (DAC), June 2015.
  12. Jian Yao, Tianshi Wang and Jaijeet Roychowdhury, "An Efficient Time Step Control Method in Transient Simulation for DAE System." in Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2014.
  13. D. Amsallem and J. Roychowdhury, “ModSpec: An Open, Flexible Specification Framework for Multi-Domain Device Modelling,” Proc. IEEE International Conference on Computer-Aided Design, Nov. 2011.



VALint: a NEEDS Verilog-A Quality Checker

VALint is a NEEDS created automatic Verilog-A script checker. It checks Verilog-A script for bad practices, common mistakes, pitfalls, and inefficiencies. VALint can also pretty-print Verilog-A code to make it tidy and more readable.

VALint is is open-source and can be downloaded here