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Compact Model Tools

Model and Algorithm Prototyping Platform (MAPP)

NEEDS is developing a platform to address the barriers to creating high-quality, physics-based compact models for emerging nanodevices. This simulation-ready, open-source, compact model development environment will be Verilog-A compliant as far as possible, but it will go beyond Verilog-A with new capabilities needed for nanodevices. It will provide a complete environment for developing, testing, experimentally validating compact models and for inserting them in commercial and open source SPICE-compatible simulation platforms.


MAPP Publications

  1. T. Wang, A. V. Karthik, B. Wu, J. Yao and J. Roychowdhury, “MAPP: The Berkeley Model and Algorithm Prototyping Platform,” Proc. IEEE Custom Integrated Circuits Conference, September 2015, to appear. (invited)
  2. D. Amsallemâ and J. Roychowdhury, “ModSpec: An Open, Flexible Specification Framework for Multi-Domain Device Modelling,” Proc. IEEE International Conference on Computer-Aided Design, Nov. 2011.

VALint: a NEEDS Verilog-A Quality Checker

The VALint is a NEEDS created automatic Verilog-A script checker. It checks the quality of the Verilog-A script for bad practices, common mistakes, pitfalls, and inefficiencies. It can also pretty-print the Verilog-A code to make it tidy and more readable.

It is available as a standalone tool here