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Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization
04 Oct 2017 | Online Presentations | Contributor(s): Chi-Shuen Lee, Saurabh Vinayak Suryavanshi, H.-S. Philip Wong
NEDS: Nano-Engineered Device Simulation Node
RRAM Models and Applications to Circuits and Systems
08 Sep 2017 | Online Presentations | Contributor(s): Haitong Li, Zizhen Jiang, H.-S. Philip Wong
Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model v. 1.0.0
25 Aug 2014 | Compact Models | Contributor(s): Zizhen Jiang, H.-S. Philip Wong
The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM. In principle, this model has no limitations on the size of the RRAM cell. The complex process of ion and vacancy migration was simplified into the growth of a single dominant filament that preserved the essential switching physics. The size of the tunneling gap (g), which is the distance between the tip of the filament and the opposite electrode, is the primary variable determining device resistance. The current conduction is exponentially dependent on the tunneling gap distance. This distance is found by calculating the growth of the gap, taking into consideration the electric field, temperature-enhanced oxygen ion migration, and local temperature due to Joule heating. In addition, stochastic and temperature-dependent filament movement (δg) is also included. The RRAM model can be instantiated directly in HSPICE netlists to explore the impacts of RRAM on the circuit performance. It is an accurate and handy tool for design exploration and verification of RRAM circuits.
4.0 out of 5 stars
16 Mar 2007 | Tools | Contributor(s): Arash Hazeghi, Tejas Krishnamohan, H.-S. Philip Wong
Resonant Tunneling Diodes: an Exercise
06 Jan 2006 | Teaching Materials | Contributor(s): H.-S. Philip Wong
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