I am a research scholar in CAIRN-the reconfigurable architectures group of IRISA in INRIA (Bretagne-Atlantique) since September 2009. The theme of the lab is 'Energy Efficient System-on-Chips'. Currently my research interests are in the ultra-low power design of SoCs. My work forms a part of overall aims and objectives of GEODES project of Information Technology for European Advancement (ITEA2) program. I obtained Bachelor of Engineering degree in Electronics and Communications Engineering from University of Mysore, India in 1998 and Master of Technology in Electrical Engineering with a major in Microelectronics from Indian Institute of Technology - Kanpur, India in 2001. From 2001 to 2009, I worked for different semiconductor companies in various roles in ASIC design. From September 2009, I am working on ultra-low power design techniques for energy efficient SoCs.