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9nm GaSb-InAs TFET Models with Doped Source Underlap for Circuit Simulations
03 Dec 2014 | Downloads | Contributor(s): Ankit Sharma, Arun Goud Akkala, Kaushik Roy
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
Brillouin Zone Viewer
0.0 out of 5 stars
25 Jan 2011 | Tools | Contributor(s): Prasad Sarangapani, Arun Goud Akkala, Sebastian Steiger, Hong-Hyun Park, Yosef Borga, Tillmann Christoph Kubis, Michael Povolotskyi, Gerhard Klimeck
Resonant Tunneling Diode Simulation with NEGF
3.5 out of 5 stars
18 Aug 2008 | Tools | Contributor(s): Hong-Hyun Park, Zhengping Jiang, Arun Goud Akkala, Sebastian Steiger, Michael Povolotskyi, Tillmann Christoph Kubis, Jean Michel D Sellier, Yaohua Tan, SungGeun Kim, Mathieu Luisier, Samarth Agarwal, Michael McLennan, Gerhard Klimeck, Junzhe Geng
1D Heterostructure Tool
3.0 out of 5 stars
04 Aug 2008 | Tools | Contributor(s): Arun Goud Akkala, Sebastian Steiger, Jean Michel D Sellier, Sunhee Lee, Michael Povolotskyi, Tillmann Christoph Kubis, Hong-Hyun Park, Samarth Agarwal, Gerhard Klimeck, James Fonseca, Archana Tankasala, Kuang-Chung Wang, Chin-Yi Chen, Fan Chen