VALint: the NEEDS Verilog-A Checker (BETA)
21 Jan 2015 | Tools | Contributor(s): Xufeng Wang, Geoffrey Coram, Colin McAndrew
Verilog-A lint and pretty printer created by NEEDS
Writing Your First Verilog-A Compact Model
13 Mar 2014 | Online Presentations | Contributor(s): Geoffrey Coram
This talk is directed at device engineers and researchers who need a SPICE-compatible compact model. The assumption is that you understand the physics of the device, you have a set of equations that describe the terminal characteristics, but you’ve never written a compact model before. Some practical advice is provided on how to write a model that is good enough for early stage circuit simulation and that can serve as a starting point for an industrial-strength compact model that circuit designers can use.
Verilog-A: Present Status and Guidelines
19 Jun 2013 | Online Presentations | Contributor(s): Geoffrey Coram
Verilog-A is the standard language for compact model development and implementation.
This talk provides some background on the rationale for and development of Verilog-A,
summarizes the current status of the language, and provides a short introduction and
some tips for writing good compact models in Verilog-A. Pointers to more extensive
references are also provided.