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VALint: the NEEDS Verilog-A Checker (BETA)
21 Jan 2015 | Tools | Contributor(s): Xufeng Wang, Geoffrey Coram, Colin McAndrew
Verilog-A lint and pretty printer created by NEEDS
Writing Your First Verilog-A Compact Model
12 Mar 2014 | Online Presentations | Contributor(s): Geoffrey Coram
This talk is directed at device engineers and researchers who need a SPICE-compatible compact model. The assumption is that you understand the physics of the device, you have a set of equations that describe the terminal characteristics, but you’ve never written a compact model before. Some...
Verilog-A: Present Status and Guidelines
14 Jun 2013 | Online Presentations | Contributor(s): Geoffrey Coram
Verilog-A is the standard language for compact model development and implementation.This talk provides some background on the rationale for and development of Verilog-A,summarizes the current status of the language, and provides a short introduction andsome tips for writing good compact models in...
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