2D Materials and Graphene: Science to Nanofunctions
04 Oct 2017 | Online Presentations | Contributor(s): Eric Pop, Saurabh Vinayak Suryavanshi
Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization
04 Oct 2017 | Online Presentations | Contributor(s): Chi-Shuen Lee, Saurabh Vinayak Suryavanshi, H.-S. Philip Wong
Top 2 shown
Stanford 2D Semiconductor (S2DS) Transistor Model
11 Aug 2018 | Contributor(s): Saurabh Vinayak Suryavanshi, Eric Pop | doi:10.4231/D39882Q1F
The Stanford 2D Semiconductor (S2DS) model is a physics-based, compact model for field-effect transistors (FETs) based on two-dimensional (2D) semiconductors such as MoS2.
Stanford 2D Semiconductor Quasi-Ballistic Transistor Compact Model
11 Aug 2018 | Contributor(s): Saurabh Vinayak Suryavanshi, Eric Pop | doi:10.4231/D3F18SH56
The S2DSb compact model is based on MVS model and captures the quasi-ballistic transport in two-dimensional field effect transistors (2D FETs). It also includes a detailed device self-heating model and temperature effects for sub-10 nm 2D FETs.
04 Apr 2016 | Contributor(s): Saurabh Vinayak Suryavanshi, Eric Pop | doi:10.4231/D3ZC7RV9X
22 Oct 2014 | Contributor(s): Saurabh Vinayak Suryavanshi, Eric Pop | doi:10.4231/D3QJ78004
Top 4 shown