Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model 1.0.0
21 Jul 2014 | Compact Models | Contributor(s): Xuanyao Fong, Sri Harsha Choday, Panagopoulos Georgios, Charles Augustine, Kaushik Roy
This is the Verilog-A model of the magnetic tunnel junction developed by the Nanoelectronics...
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si...
SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation
21 Aug 2013 | Downloads | Contributor(s): Xuanyao Fong, Sri Harsha Choday, Panagopoulos Georgios, Charles Augustine, Kaushik Roy
Models for simulating a magnetic tunnel junction in HSPICE. The usage description is included in...
PETE : Purdue Emerging Technology Evaluator
26 Jun 2007 | Tools | Contributor(s): Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, Kaushik Roy
Estimate circuit level performance and power of novel devices
Design in the Nanometer Regime: Process Variation
28 Nov 2006 | Online Presentations | Contributor(s): Kaushik Roy
Scaling of technology over the last few decades has produced an exponential growth in computing...