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PETE : Purdue Emerging Technology Evaluator
26 Jun 2007 | Tools | Contributor(s): Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, Kaushik Roy
Estimate circuit level performance and power of novel devices
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Design in the Nanometer Regime: Process Variation
28 Nov 2006 | Online Presentations | Contributor(s): Kaushik Roy
Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in …
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Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance
28 Nov 2006 | Online Presentations | Contributor(s): Kaushik Roy
The scaling of technology has produced exponential growth in transistor development and computing power in the last few decades, but scaling still presents several challenges. These two lectures will cover device aware CMOS design to address power, reliability, and process variations in scaled …
