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  • Organization
    Stanford University

  • Employment Type
    university

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  • Biography

    H.-S. Philip Wong received the B.Sc. (Hons.) in 1982 from the University of Hong Kong, the M.S. in 1983 from the State University of New York at Stony Brook, and the Ph.D. in 1988 from Lehigh University, all in electrical engineering. He joined the IBM T. J. Watson Research Center, Yorktown Heights, New York, in 1988. In September, 2004, he joined Stanford University as Professor of Electrical Engineering.

    While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM's strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.

    His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging. He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronics systems. Novel devices often require new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven. His present research covers a broad range of topics including carbon nanotubes, semiconductor nanowires, self-assembly, exploratory logic devices, and novel memory devices.

    He is a Fellow of the IEEE and serves on the IEEE Electron Devices Society (EDS) as elected AdCom member. He serves on the IEDM committee from 1998 to 2006 and is the Technical Program Chair in 2006. He served on the ISSCC program committee from 1998 - 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. He is the Editor-in-Chief of the IEEE Transactions on Nanotechnology. He is a Distinguished Lecturer of the IEEE EDS and Solid-State Circuit Society. He has taught several short courses at the IEDM, ISSCC, Symp. VLSI Technology, SOI conference, ESSDERC, and SPIE conferences. He is a member of the Emerging Research Devices Working Group of the International Technology Roadmap for Semiconductors (ITRS).


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