Switching Energy in CMOS Logic: How far are we from physical limit?
24 Apr 2006 | Online Presentations | Contributor(s): Saibal Mukhopadhyay
Aggressive scaling of CMOS devices in technology generation has resulted in exponential growth in device performance, integration density and computing power. However, the power dissipated by a silicon chip is also increasing in every generation and emerging as a major bottleneck to technology scaling in nanometer technologies. Hence, analysis and reduction of switching energy in binary logic has drawn significant research interest in recent years.