III-V Tunnel FET Model 1.0.1

By Huichu Liu1, Vinay Saripalli1, Vijaykrishnan Narayanan1, Suman Datta1

Penn State University

The III-V Tunnel FET Model is a look-up table based model, where the device current and capacitance characteristics are obtained from calibrated TCAD Sentaurus simulation.

Listed in Compact Models | publication by group NEEDS: New Era Electronic Devices and Systems

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Version 1.0.1 - published on 21 Apr 2015 doi:10.4231/D30Z70X8D - cite this

Licensed under NEEDS Modified CMC License according to these terms

Description

The III-V Tunnel FET Model is a look-up table based model, where the device current and capacitance characteristics are obtained from calibrated TCAD Sentaurus simulation. Verilog-A models for two types of III-V Tunnel FET, InAs Homojunction Tunnel FET and GaSb-InAs Heterojunction Tunnel, are included.

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Notes

Dear Users,

The following changes have been made to III-V Tunnel FET Model Version 1.0.1 compared to the previous Version 1.0.0:

(1) tfet_master.va combined all the model features for n-type and p-type homojunction and heterojunction TFETs. 'ifdef has been used to enable HOMOJUNCTION and HETEROJUNCTION features.

(2) homotfet.va and heterotfet.va call tfet_master.va to enable different types of TFETs (e.g. InAs Homojunction TFET and GaSb-InAs Heterojunction TFET).

(3) A parameter "type" has been added into the tfet_master.va file to define n-type and p-type transistors, which needs to be specify in circuit netlist. 

Please see the updated manual Section 3 & 4 for details.

Sincerely,

Huichu Liu

April 20, 2015.