MIT Virtual Source Negative Capacitance (MVSNC) model 1.0.0

By Ujwal Radhakrishna1, Asif Islam Khan2, Sayeef Salahuddin2, Dimitri Antoniadis1

1. Massachusetts Institute of Technology (MIT) 2. University of California, Berkeley

MIT Virtual Source Negative FET (MVSNC) model is a compact model for negative capacitance transistors that use a FE-oxide in the gate stack to achieve internal voltage amplification and steep subthreshold swing.

Listed in Compact Models

Download Bundle

Additional materials available

Version 1.0.0 - published on 06 Mar 2017 doi:10.4231/D3K649T9T - cite this

Licensed under NEEDS Modified CMC License according to these terms

ncfet.jpg

Description

MIT Virtual Source Negative FET (MVSNC) model is a compact model for negative capacitance transistors that use a FE-oxide in the gate stack to achieve internal voltage amplification and steep subthreshold swing. 

The model uses MVS model for underlying Si-FET which is calibrated against Intel 45-nm devices released in MVS-1 release (Shaloo Rakheja et.al, doi:10.4231/D3RR1PN6M) and Landau-Khalatnikov (L-K) equation to capture the static and dynamic behavior of FE-oxide. The work extends the earlier release on NCFETs in the MVS framework by Muhammad Abdul Wahab et.al, (doi:10.4231/D3PV6B79V) by including the dynamics of FE-leakage and work-function engineering (WFE) to mitigate its effects in transient device operation.

The release includes the Verilog-A code for N-channel and P-channel NCFETs that use Intel 45-nm underlying CMOS transistors and HZO-based FE-oxide in the gate-stack. The release also includes device simulations of transient IVs and CVs that can be used to test the impact of dielectric leakage on the performance of NCFETs. Further the advantage of NCFETs in terms of energy-delay can be tested at the circuit-level using inverters and inverter chain simulations. The benchmark circuits are implemented in Advanced Design System (ADS) platform and included in the release.

The simulations verify the performance of (i) baseline FETs (ii) Nominal NCFETs (without leakage or WFE) (iii) Leaky nominal NCFET (leakage without WFE) and (iv) Leakage-aware NCFETs (with leakage and WFE) in transient device and circuit simulations to study the performance benefits of this emerging technology.

Model Release Components ( Show bundle contents ) Bundle

Key References

- A. I. Khan, U. Radhakrishna, K. Chatterjee, S. Salahuddin and D. A. Antoniadis, "Negative Capacitance Behavior in a Leaky Ferroelectric," in IEEE Transactions on Electron Devices, vol. 63, no. 11, pp. 4416-4422, Nov. 2016.

-A. I. Khan, U. Radhakrishna, K. Chatterjee, S. Salahuddin and D. A. Antoniadis, “Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs” submitted to Electron Device Lett. 2017.

 

Cite this work

Researchers should cite this work as follows:

Tags