To gain more insights into the benefits of tunnel FETs in low power circuit applications and make performance projections, a universal analytical TFET compact model that captures the essential features of the tunneling process has been developed. The model is valid in all four operating quadrants of the TFET. Based on the Kane-Sze formula for tunneling, the model captures the distinctive features of TFETs such as bias-dependent subthreshold swing, superlinear drain current onset, ambipolar conduction, and negative differential resistance (NDR). To guarantee charge conservation an analytic charge-based capacitance model of the terminal capacitances has also been developed. A bias dependent gate current model with a 100%/0% drain/source current partition is also included. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. The model is implemented in Verilog-A and in AIM-Spice that is available on macOS, Windows, Android, Linux and iOS.
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 H. Lu, J. W. Kim, D. Esseni, and A. Seabaugh, "Continuous semiempirical model for the current-voltage characteristics of tunnel FETs," in Proc. 15th Int. Conf. ULIS, 2014, pp. 25-28.
 H. Lu, D. Esseni, and A. Seabaugh, "Universal analytic model for tunnel FET circuit simulation," Solid-State Electronics, vol. 108, pp. 110-117, June 2015.
 H. Lu, W. Li, Y. Lu, P. Fay, T. Ytterdal and A. Seabaugh, "Universal charge-conserving TFET SPICE model incorporating gate current and noise," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, pp. 20-27, July 2016.
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