Universal TFET model 1.6.8

By Hao Lu1, Trond Ytterdal2, Alan Seabaugh1

1. University of Notre Dame 2. Norwegian University of Science and Technology

A universal TFET compact model implemented in verilog-A

Listed in Compact Models | publication by group NEEDS: Nano-Engineered Electronic Device Simulation Node

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Version 1.6.8 - published on 26 Jan 2015 doi:10.4231/D3901ZG9H - cite this

Licensed under NEEDS Modified CMC License according to these terms

Description

To gain more insights into the benefits of tunnel FETs in low power circuit applications and make performance projections, a universal analytical TFET SPICE model that captures the essential features of the tunneling process has been developed. The model is valid in all four operating quadrants of the TFET. Based on the Kane-Sze formula for tunneling, the model captures the distinctive features of TFETs such as bias-dependent subthreshold swing, superlinear drain current onset, ambipolar conduction, and negative differential resistance (NDR). A simple analytic capacitance model of the gate drain capacitance has also been developed and validated on two different TFET structures: a planar InAs double-gate TFET and an AlGaSb/InAs in-line TFET, and good agreement is observed between the model and published simulations. The model is implemented in SPICE simulators using Verilog-A and in native AIM-Spice, available on Mac, Windows, Android, and iOS. 

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Key References

1. H. Lu, J. W. Kim, D. Esseni, and A. Seabaugh, “Continuous semiempirical model for the current-voltage characteristics of tunnel FETs,” in Proc. 15th Int. Conf. ULIS, 2014, pp. 25-28.

2. H. Lu, D. Esseni, and A. Seabaugh, “Universal analytic model for tunnel FET circuit simulation,” Solid-State Electronics, 2015, in press.

 

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Notes

Initial version for NEEDS.