Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model 1.0.1

By Chi-Shuen Lee1, H.-S. Philip Wong1

Stanford University

The VSCNFET model captures the dimensional scaling properties and includes parasitic resistance, capacitance, and tunneling leakage currents. The model aims for CNFET technology assessment for the sub-10-nm technology nodes.

Listed in Compact Models | publication by group NEEDS: New Era Electronic Devices and Systems

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Version 1.0.1 - published on 09 Apr 2015 doi:10.4231/D3BK16Q68 - cite this

Licensed under NEEDS Modified CMC License according to these terms

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Description

See more compact models using the MIT Virtual Source (MVS) Model

The Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors (VSCNFET) model is a semi-empirical compact model for CNFETs that captures the dimensional scaling properties and includes parasitic resistance, capacitance, and tunneling leakage currents. Inputs to the model are device design parameters such as gate length, gate oxide thickness, CNT diameter, and flat-band voltage. Experimental devices with the gate length down to 15 nm and numerical simulations based on the non-equilibrium Green’s function formalism are used for parameter extraction and model calibration. The model aims to assess the potentials of CNFET technology for the sub-10-nm technology nodes.

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Key References

C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, “A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part I: Intrinsic Elements,” arXiv:1503.04397

C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, “A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part II: Extrinsic Elements and Performance Assessment,” arXiv:1503.04398

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Notes

Updates in version 1.0.1

1) Modified the charge model to avoid differentiation problem at Vds = 0

2) Removed unused and duplicate variables and hidden states in the Verilog-A file

3) Changed module name to vscnfet_1_0_1 to match with the Verilog-A file name vscnfet_1_0_1.va

4) Changed limexp() to exp() in all the non-genvar for-loops

5) Initialized the surface potential psys in the Verilog-A file