Useful macros and analog function building blocks for compact models.
Many aspects of compact models for different semiconductor devices are the same: pn-junctions form a part of most components, either as intrinsic to the device or as parasitics; declaration of parameters, limiting and clamping of parameters, and interaction with simulator variables like gmin and scale is required in Verilog-A. To help converge to a common coding style, avoid duplication of effort if every model developer has to redevelop and code the same aspects of a model, and help adoption of known best practices, two collections of Verilog-A primitives (macros and analog functions) are provided.
The first of these, general.va, comprises macros for: clamping, smooth limiting, parameter specification, simulator variable handling, controlled limited exponential evaluation, numerically stable modeling of resistors including node collapse if the resistance is zero, and other miscellaneous items. The second is junction.va, which contains analog functions for pn-junction charge (including area and perimeter components), junction breakdown, junction current (including area and perimeter components), junction built-in potential mapping as a function of temperature (that is physically correct and does not become negative for high temperatures), and a macro for junction shot noise that is more accurate than 2qI for biases around zero.
This document details the contents of both of these collections of Verilog-A primitives. The names of the files are general_vV_S_R.va andjunction_vV_S_R.va, where V, S, and R are the version, subversion, and release numbers. Explicit numbering is included as part of the file name so that any updates will not affect the behavior of a model that uses any of the provided primitives.
Model Release Components ( Show bundle contents ) Bundle
- General and Junction Primitives for Verilog-A Compact Models 1.0.0 Verilog-A(ZIP | 9 KB)
- General and Junction Primitives for Verilog-A Compact Models 1.0.0 Benchmarks(ZIP | 50 KB)
- HTML documentation for the general and junction Verilog-A primitives.(GZ | 171 KB)
- v1_0_0.tar.gz (complete code, benchmark tests and results, and documentation)(GZ | 226 KB)
- License terms
Cite this work
Researchers should cite this work as follows:
- McAndrew, C., Coram, G. (2015). General and Junction Primitives for Verilog-A Compact Models. nanoHUB. doi:10.4231/D3G15TC2J
Initial version, derived from macros used in R3 converted to analog functions and cleaned up.
NEEDS: New Era Electronic Devices and Systems
This publication belongs to the NEEDS: New Era Electronic Devices and Systems group.