A Verilog-A Compact Model for Negative Capacitance FET 1.1.0

By Muhammad Abdul Wahab1, Muhammad A. Alam1

Purdue University

The NC-FET compact model is a semi-physical verilog-A model of the negative capacitance transistor. We developed this self-consistent model with BSIM4/MVS and Landau theory. This model is useful to design NC-FET for high speed and low power...

Listed in Compact Models | publication by group NEEDS: Nano-Engineered Electronic Device Simulation Node

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Version 1.1.0 - published on 07 Apr 2016 doi:10.4231/D3PV6B79V - cite this

Licensed under NEEDS Modified CMC License according to these terms

Description

The NC-FET compact model is a semi-physical verilog-A  model of the negative capacitance transistor. In the model, NC dielectric is integrated as gate dielectric stack with conventional MOSFET . The NC dielectric is explained by Landau theory and the conventional MOSFET is represented by available models of MOSFET such as MVS and BSIM4. The two elements work self-consistently to provide the characteristics of NC-FET. The model works for both short and  long channel transistors. Using the NC-FET model in HSPICE, performance of the complex circuits can be evaluated. The model can be adapted to include multiple layers of NC-dielectric stack and new conventional  MOSFET model with necessary modifications. This model is useful to design and optimize the performance of NC-FET with a goal for high speed and low power applications.

Additional Resources

A Tutorial Introduction to Negative-­Capacitor Landau Transistors: Perspectives on the Road Ahead 

A MATLAB script to implements the concepts behind this compact model is also available here as well as a list of resources for Landau switches.

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