A Verilog-A Compact Model for Negative Capacitance FET 1.1.1
The NC-FET compact model is a semi-physical verilog-A model of the negative capacitance transistor. We developed this self-consistent model with BSIM4/MVS and Landau theory. This model is useful to design NC-FET for high speed and low power...
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Version 1.1.1 - published on 10 Mar 2017 doi:10.4231/D30863660 - cite this Last public release: 1.1.3
Licensed under NEEDS Modified CMC License according to these terms
Description
The NC-FET compact model is a semi-physical verilog-A model of the negative capacitance transistor. In the model, NC dielectric is integrated as gate dielectric stack with conventional MOSFET . The NC dielectric is explained by Landau theory and the conventional MOSFET is represented by available models of MOSFET such as MVS and BSIM4. The two elements work self-consistently to provide the characteristics of NC-FET. The model works for both short and long channel transistors. Using the NC-FET model in HSPICE, performance of the complex circuits can be evaluated. The model can be adapted to include multiple layers of NC-dielectric stack and new conventional MOSFET model with necessary modifications. This model is useful to design and optimize the performance of NC-FET with a goal for high speed and low power applications.
See also: MIT Virtual Source Negative Capacitance (MVSNC) model
The Purdue NC-FET model is modular with separate implementations for the FE model and for the MOSFET model (either MVS or BSIM). With slight modifications to the MOSFET models, it is possible to hook the modules together and have a composite NC-FET model. MVSNC on the other hand is integrated, i.e. there are no extra nodes for the NC-FET model. The integration may make MVSNC run faster for large circuits.
Additional Resources
A Tutorial Introduction to Negative-Capacitor Landau Transistors: Perspectives on the Road Ahead
A MATLAB script to implements the concepts behind this compact model is also available here as well as a list of resources for Landau switches.
Model Release Components ( Show bundle contents ) Bundle
A Verilog-A Compact Model for Negative Capacitance FET 1.1.1 Verilog-A(ZIP | 34 KB)- A Verilog-A Compact Model for Negative Capacitance FET 1.1.1 Benchmarks(ZIP | 3 MB)
- A Verilog-A Compact Model for Negative Capacitance FET 1.1.1 Parameters(ZIP | 6 KB)
- A Verilog-A Compact Model for Negative Capacitance FET 1.1.1 Experimental Data(ZIP | 612 B )
A Verilog-A Compact Model for Negative Capacitance FET 1.1.1 Manual(PDF | 1 MB)- License terms
Cite this work
Researchers should cite this work as follows:
- Muhammad Abdul Wahab; Muhammad A. Alam (2017). A Verilog-A Compact Model for Negative Capacitance FET. (Version 1.1.1). nanoHUB. doi:10.4231/D30863660