The NC-FET compact model is a semi-physical verilog-A  model of the negative capacitance transistor. In the model, NC dielectric is integrated as gate dielectric stack with conventional MOSFET . The NC dielectric is explained by Landau theory and the conventional MOSFET is represented by available models of MOSFET such as MVS and BSIM4. The two elements work self-consistently to provide the characteristics of NC-FET. The model works for both short and  long channel transistors. Using the NC-FET model in HSPICE, performance of the complex circuits can be evaluated. The model can be adapted to include multiple layers of NC-dielectric stack and new conventional  MOSFET model with necessary modifications. This model is useful to design and optimize the performance of NC-FET with a goal for high speed and low power applications.

See also: MIT Virtual Source Negative Capacitance (MVSNC) model

The Purdue NC-FET model is modular with separate implementations for the FE model and for the MOSFET model (either MVS or BSIM). With slight modifications to the MOSFET models, it is possible to hook the modules together and have a composite NC-FET model. MVSNC on the other hand is integrated, i.e. there are no extra nodes for the NC-FET model. The integration may make MVSNC run faster for large circuits.

Additional Resources

A Tutorial Introduction to Negative-­Capacitor Landau Transistors: Perspectives on the Road Ahead 

A MATLAB script to implements the concepts behind this compact model is also available here as well as a list of resources for Landau switches.

• A Verilog-A Compact Model for Negative Capacitance FET 1.1.0 Verilog-A(ZIP | 35 KB)
• A Verilog-A Compact Model for Negative Capacitance FET 1.1.0 Benchmarks(ZIP | 3 MB)
• A Verilog-A Compact Model for Negative Capacitance FET 1.1.0 Parameters(ZIP | 6 KB)
• A Verilog-A Compact Model for Negative Capacitance FET 1.1.0 Experimental Data(MAT | 470 B )
• A Verilog-A Compact Model for Negative Capacitance FET 1.1.0 Manual(PDF | 874 KB)
• License terms

1. M. A. Wahab, S. Shin, and M. A. Alam, “3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3595–3604, Nov. 2015.
2. S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices.,” Nano Lett., vol. 8, no. 2, pp. 405–10, Feb. 2008. A. Jain and M. A. Alam, “Stability Constraints Define the Minimum Subthreshold Swing of a Negative Capacitance Field-Effect Transistor,” IEEE Trans. Electron Devices, vol. 61, no. 7, pp. 2235–2242, Jul. 2014.
3. A. Jain and M. A. Alam, “Proposal of a Hysteresis-Free Zero Subthreshold Swing Field-Effect Transistor,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3546–3552, Oct. 2014. A. Jain and M. A. Alam, “Prospects of Hysteresis-Free Abrupt Switching (0 mV/decade) in Landau Switches,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4269–4276, Dec. 2013.
4. K. Karda, A. Jain, C. Mouli, and M. A. Alam, “An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed,” Appl. Phys. Lett., vol. 106, no. 16, p. 163501, Apr. 2015.
5. Y. Li, Y. Lian, K. Yao, and G. S. Samudra, “Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory,” Solid. State. Electron., vol. 114, pp. 17–22, Dec. 2015.
6. M. A. Wahab and M. A. Alam, “Compact Model of Short-Channel Negative Capacitance (NC)-FET with BSIM4/MVS and Landau Theory,” in NEEDS Annual Meeting and Workshop, May 11-12, 2015, Cambridge, MA, USA.
7. M. A. Alam, P. Dak, M. A. Wahab, and X. Sun, “Physics-Based Compact Models for Insulated-Gate Field-Effect Biosensors, Landau Transistors, and Thin-Film Solar Cells,” in IEEE Custom Integrated Circuits Conference (CICC), September 28-30, 2015, San Jose, CA, USA.
8. S. Rakheja and D. Antoniadis, “MVS Nanotransistor Model (Silicon),” nanoHUB.

Researchers should cite this work as follows:

• Muhammad Abdul Wahab; Muhammad A. Alam (2016). A Verilog-A Compact Model for Negative Capacitance FET. (Version 1.1.0). nanoHUB. doi:10.4231/D3PV6B79V

  BibTex | EndNote

This revised verilog-A version (1.1.0) of NC-FET includes (i) dipole response of the NC dielectric in transient simulation, (ii) explicit definition of all variables (1.0.0), and (iii) a modified expression for I_D leakage to ensure that MVS model produces  I_D=0 µA/µm at V_D=0 V. The selector ‘leak_select’ allows the user to include or exclude the I_D leakage current.