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A methodology for SPICE-compatible modeling of nanoMOSFETs

By Alba Graciela Avila1, David Espejo2

1. Universidad de los Andes 2. Microelectronics Center, University of the Andes

Published on

Abstract

course51285 An original SPICE-compatible model for Intel's 45nm High-K MOSFET is presented. It takes into account some Quantum-Mechanical Effects that occur at small scale like Channel Length Modulation (CLM), Threshold Voltage variation and Velocity saturation, and is the first in his class that is not fully based on ASU's Predictive Technology Model, but incorporates device parameters to fully simulate process variation effects on MOSFET behavior. The model expressions are found first by obtaining and validating a model for the carrier quantization phenomenon in the region near the Si/HfO2 interface because the effects associated with that particular phenomenon determine the device behavior in a downscaling scenario. Precision of that model, allowed finding equations for the device's compact I-V model. The shortest gate length (Lg) at which SPICE can simulate MOSFET behavior with close relationship with expected values in SPICE3-based Orcad PSPICE™ 9.1 is determined, and a SCORM object has been developed to assist the learning of this modeling methodology.

Bio

Prof. Alba Ávila, PhD. Associate Professor, Department of Electrical and Electronics Engineering, University of the Andes. Director of the Micro and Nano Technologies Research Group, Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia
David Espejo: Electronics Engineer, Universidad Distrital, Member of Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia

Credits

Microelectronics Center, Universidad de los Andes (CMUA) - Universidad de los Andes, Bogota, Colombia

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References

[1]G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, No. 8. 1965
[2]K. Mistry, C. Allen, C. Auth., "A 45 nm logic technology with High-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning and 100% free Pb packaging", IEDM, 2007.
[3]Intel, "Technology at Intel:January 2010 Archive". Available on http://blogs.intel.com/technology/2010/01/ retrieved on 11/17/10
[4]T. Morshed, et. al., "BSIM 4.6.4 MOSFET Model: User' Manual", University of California, Berkeley, 2009.
[5]D. Vasileska, S. Ahmed, M. Mannino, A. Matsudaira, G. Klimeck, M. Lundstrom, SCHRED, available on http://nanohub.org/resources/schred
[6]L. Wang, "Quantum mechanical effects on MOSFET scaling limit", thessis for the PhD degree, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2006.
[7]Z. Ren, "Nanoscale MOSFETs: Physics, simulation and design", thessis for the PhD degree, Purdue University, 2001.
[8]University of California, Berkeley, Arizona State University, Berkeley Predictive Technology Model, available on http://ptm.asu.edu/modelcard/LP/45nm_LP.pm, retrieved on 26/04/10

Cite this work

Researchers should cite this work as follows:

  • Alba Graciela Avila; David Espejo (2010), "A methodology for SPICE-compatible modeling of nanoMOSFETs," http://nanohub.org/resources/10024.

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