A methodology for SPICE-compatible modeling of nanoMOSFETs

By Alba Graciela Avila1, David Espejo2

1. Universidad de los Andes 2. Microelectronics Center, University of the Andes

Published on


course51285 An original SPICE-compatible model for Intel's 45nm High-K MOSFET is presented. It takes into account some Quantum-Mechanical Effects that occur at small scale like Channel Length Modulation (CLM), Threshold Voltage variation and Velocity saturation, and is the first in his class that is not fully based on ASU's Predictive Technology Model, but incorporates device parameters to fully simulate process variation effects on MOSFET behavior. The model expressions are found first by obtaining and validating a model for the carrier quantization phenomenon in the region near the Si/HfO2 interface because the effects associated with that particular phenomenon determine the device behavior in a downscaling scenario. Precision of that model, allowed finding equations for the device's compact I-V model. The shortest gate length (Lg) at which SPICE can simulate MOSFET behavior with close relationship with expected values in SPICE3-based Orcad PSPICE™ 9.1 is determined, and a SCORM object has been developed to assist the learning of this modeling methodology.


Prof. Alba Ávila, PhD. Associate Professor, Department of Electrical and Electronics Engineering, University of the Andes. Director of the Micro and Nano Technologies Research Group, Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia
David Espejo: Electronics Engineer, Universidad Distrital, Member of Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia


Microelectronics Center, Universidad de los Andes (CMUA) - Universidad de los Andes, Bogota, Colombia

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Cite this work

Researchers should cite this work as follows:

  • Alba Graciela Avila, David Espejo (2010), "A methodology for SPICE-compatible modeling of nanoMOSFETs," http://nanohub.org/resources/10024.

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