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Prof. Alba Ávila, PhD. Associate Professor, Department of Electrical and Electronics Engineering, University of the Andes. Director of the Micro and Nano Technologies Research Group, Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia
David Espejo: Electronics Engineer, Universidad Distrital, Member of Microelectronics Center, University of the Andes (CMUA), Bogota, Colombia
Microelectronics Center, Universidad de los Andes (CMUA) - Universidad de los Andes, Bogota, Colombia
G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, No. 8. 1965
K. Mistry, C. Allen, C. Auth., "A 45 nm logic technology with High-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning and 100% free Pb packaging", IEDM, 2007.
Intel, "Technology at Intel:January 2010 Archive". Available on http://blogs.intel.com/technology/2010/01/ retrieved on 11/17/10
T. Morshed, et. al., "BSIM 4.6.4 MOSFET Model: User' Manual", University of California, Berkeley, 2009.
D. Vasileska, S. Ahmed, M. Mannino, A. Matsudaira, G. Klimeck, M. Lundstrom, SCHRED, available on http://nanohub.org/resources/schred
L. Wang, "Quantum mechanical effects on MOSFET scaling limit", thessis for the PhD degree, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2006.
Z. Ren, "Nanoscale MOSFETs: Physics, simulation and design", thessis for the PhD degree, Purdue University, 2001.
University of California, Berkeley, Arizona State University, Berkeley Predictive Technology Model, available on http://ptm.asu.edu/modelcard/LP/45nm_LP.pm, retrieved on 26/04/10
Researchers should cite this work as follows:
Alba Graciela Avila; David Espejo (2010), "A methodology for SPICE-compatible modeling of nanoMOSFETs," https://nanohub.org/resources/10024.