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Tunneling in an Nanometer-Scaled Transistor

By Gerhard Klimeck1, Mathieu Luisier1, Neerav Kharche1, George A. Howlett2, Insoo Woo3, David Ebert1

1. Electrical and Computer Engineering, Purdue University, West Lafayette, IN 2. HUBzero, Purdue University, West Lafayette, IN 3. Purdue University, West Lafayette, IN



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Electrons tunneling through the gate of an ultra-scaled transistor.

Tunneling in an Nanometer-Scaled Transistor The continued down-scaling of transistors has enabled tremendous advances in consumer electronics. We are reaching the limits where individual transistors or on-off electron valves are only a few nanometers in diameters wide. At these atomic length scales the electrons no longer act like billiard balls but rather like waves. As a result, electrons can tunnel through forbidden device regions, causing additional conduction and heat generation paths. Sophisticated modeling engines that consider a quantum mechanical description of the electrons, an atomistic description of the material, and non-equilibrium electron distributions, are needed for device design and optimization.

The "OMEN_FET" tool on enables such device modeling, and allows for the visualization of the electron density in such ultra-scaled structures through 3D volume rendering.

The current density was computed with the OMEN_FET tool and visualized with the nanoVIZ tool on



Cite this work

Researchers should cite this work as follows:

  • Gerhard Klimeck; Mathieu Luisier; Neerav Kharche; George A. Howlett; Insoo Woo; David Ebert (2011), "Tunneling in an Nanometer-Scaled Transistor,"

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