Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (2011)
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Abstract
This is a presentation on Negative Bias Temperature Instability, or in short NBTI, observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON gate insulators in order to keep up with Moore's scaling law. The issue is still relevant and also very much exits in the recently introduced HiK gate stacks.
In this talk, I will start with a brief introduction to NBTI and show some important features. This will be followed by the description of an ultra-fast NBTI characterization method that we have developed. We have extensively used this method to study NBTI parametric degradation in FETs having a wide variety of gate insulator processes and this will be covered next. As we shall see, NBTI is strongly gate insulator process dependent and this is a crucial information to understand the underlying physical mechanism of NBTI and its optimization via suitable process changes. Information obtained from other characterization methods such as flicker noise, DCIV, charge pumping about process related pre-existing defects and stress generated defects will be covered next. This will bring us to the description of NBTI physical mechanism, which I will discuss with an aim of developing a predictive model for lifetime determination under use condition.
I will conclude the talk with the following take home messages. NBTI stress results in generation of interface traps together with hole trapping in process related pre-existing bulk oxide traps as well as in stress generated bulk oxide traps. Though there is some differences in generated interface and bulk traps, the process related pre-existing defects are primarily responsible for large difference in NBTI magnitude, time and temperature dependence seen in differently processed devices. NBTI can be improved by suitable process modifications that reduces these pre-existing defects. Bulk trap generation is significant at higher stress bias, but due to its stronger voltage acceleration, it becomes relatively negligible, though not zero, at use conditions. The interface trap contribution shows a strong universality in terms of DC and AC degradation, and is primarily responsible for long-time failure at use condition. Finally, once the hole trap contribution is taken into account, the Reaction-Diffusion model can successfully predict DC and AC NBTI results governed by contribution from interface traps.
Bio
Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, India, in 1999. He was at Bell Laboratories, Murray Hill, NJ, USA during 2000-2001. Since 2002 he is with the Department of Electrical Engineering, IIT Bombay, India, and presently holds the position of Professor. His research interests are in the area of characterization, modeling and simulation of CMOS and Flash memory devices, solar cells, and device reliability. He has published more than 100 papers in international journals and conferences, delivered invited talks at leading international conferences in the USA, Europe and Asia-pacific including at IEEE IEDM, delivered reliability tutorials at IEEE IRPS, and acted as a reviewer of several international journals and conferences. He also holds an honorary graduate faculty position at Purdue University, USA, is a distinguished lecturer of IEEE EDS, a senior member of the IEEE and a fellow of the Indian National Academy of Engineering. Credits
Co-contributors: M. A. Alam & A. E. Islam (Purdue), E. N. Kumar, V. D. Maheta, S. Deora, G. Kapila, D. Varghese & K. Joshi (IIT Bombay), C. Olsen and K. Ahmed (Applied Materials)
Acknowledgement: CEN IIT Bombay, NCN Purdue, Applied Materials, Renesas Electronics, SRC / GRC
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