Nanotechnology comprises the techniques for making things small (<100 nm) — i.e., nanopatterning — and the resulting applications, ranging from the results of undirected nanopatterning such as Goretex, paint, and reactive gold nanoparticles, to those of directed nanopatterning such as semiconductor and photonic circuits and genomic microarrays. Fanciful extensions to useful nanorobots and nanorotating machinery can be discarded, certainly for my lifetime and probably forever.
Nanotechnology predates the NNI by several decades. The late 1950s saw the invention of the integrated circuit, the landmark papers by Buck and Shoulders and by Feynman, and early examples of nanopatterning by Moellenstedt. I "wrote" a 10-nm feature in 1963. In the early 1970s, the quantitative advantages of scaling electronic circuits to smaller dimensions were formalized, and fabricating vertical structures to monolayer precision through molecular-beam epitaxy and Langmuir Blodgett technology became accepted techniques. Also in the 1970s, electron beam lithography became a standard technique for pattern generation and demonstrated features down to 5 nm. The throughput limitations of this technique also became apparent. The National Science Foundation set up the National Submicron facility during this time as well, and the facility has now morphed into the National Nanotechnology Infrastructure Network.
Nanopatterning has paid off spectacularly for semiconductor circuitry. As features are scaled down, the speed of a given circuit has increased linearly and the energy per computing function has decreased as the cube of the scaling factor. Unfortunately, the equipment now being developed for semiconductors is too expensive and too specialized for other applications. The next generation ("45-nm node") of semiconductor circuit patterning tools will cost $30 million and can only accommodate 300-mm diameter silicon wafers partially immersed in water. Alternative nanofabrication techniques include nanoprinting, which has evolved into a variety of techniques with capabilities to replicate 10-nm features at about 1 cm2/s.
What is still missing is the ability to make and inspect the necessary templates economically. I have some ideas — a few of them borrowed from the disk storage industry. We also need to be able to place the patterns to sub-10 nm precision and ensure the absence of defects. A related challenge is how to fabricate nanostructures on non-flat (e.g., doubly curved) surfaces. Non-directed patterning, such as self-assembly techniques, can help by rapidly filling in specified areas with nano structures on the sub-25 nm scale. When we meet all of these challenges, we will have even more opportunities for pushing nanotechnology into a wide variety of applications.
R. Fabian Pease is the William Ayer Professor of Electrical Engineering at Stanford University. He has been a professor at Stanford since 1978 and was appointed to his current position in 2001.
His group’s areas of research include micro- and nano-fabrication and their application to electronic and magnetic devices and structures. Among other achievements, this work has included the original demonstration of lithography with the scanning tunneling microscope and the invention of the micro-channel heat sink.
While on sabbatical in 1993 and 1994, Pease conducted research on the synthesis of DNA microarrays at Affymetrix Corporation. From 1996 to 1998, he was assigned to the Defense Advanced Research Projects Agency, where he initiated programs in advanced microelectronics and molecular-level printing. He has also served as a consultant to IBM, Xerox, Etec Systems, and Lawrence Livermore Labs, and is on the technical advisory boards of Ultratech Stepper and Affymetrix.
Pease is a fellow of the IEEE and has served the association in a variety of capacities. He is also a member of the National Academy of Engineering. With his student David Tuckerman, he received the fi rst IEEE Paul Rappaport Award. He received the IEEE Cledo Brunetti Award in 2001 for advancing high-resolution patterning technologies, high-performance thermal management, and scanning electron microscopy for microelectronics. His other honors include the Richard P. Feynman Prize for Microfabrication, which he shared with his student Tom Newman, for writing a page of text in a 6-micron square with 25 nm linewidths; and a Title A Fellowship from Trinity College, Cambridge. He has published more than 200 articles and authored several book chapters.
Pease holds BA, MA, and PhD degrees from Cambridge University. His PhD thesis was on high-resolution scanning electron microscopy. Earlier in his career, Pease served as a radar offi cer in the Royal Air Force and as an assistant professor of electrical engineering at UC Berkeley. He also served on the technical staff of Bell Laboratories, where he fi rst worked on digital television and later led a group that developed processes for electron beam lithographic mask manufacture, and demonstrated a pioneering LSI circuit built with electron beam lithography.
Researchers should cite this work as follows:
(2006), "Nanofabrication," http://nanohub.org/resources/1223.
Fowler Hall, Purdue University