Switching Energy in CMOS Logic: How far are we from physical limit?

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Aggressive scaling of CMOS devices in technology generation has resulted in exponential growth in device performance, integration density and computing power. However, the power dissipated by a silicon chip is also increasing in every generation and emerging as a major bottleneck to technology scaling in nanometer technologies. Hence, analysis and reduction of switching energy in binary logic has drawn significant research interest in recent years.

Physical analysis of a binary system shows that, a binary switching can be achieved by dissipating energy as low as kBTln(2). However, International Technology Roadmap for Semiconductor suggests that, a minimum size inverter designed in 45nm node will take approximately 40,000kBT to switch. This talk will discuss the basic principles of CMOS switching from the circuit/system perspective to analyze the above difference between the physical limit of switching energy and its practical value.


Saibal Mukhopadhyay is a PhD candidate in School of Electrical and Computer Engineering at Purdue University. He received B.S. degree in electronics and telecommunication engineering from Jadavpur University, India, in 2000. His research interests include modeling and analysis of nanoscale silicon/non-silicon devices, and technology-circuit co-design methodologies for low-power and robust VLSI systems in nanometer technologies. He (co)-authored over 50 papers in refereed journals and conferences and (co)-invented 5 US patents (filed). Saibal has worked at IBM T. J. Watson Research Center for three summers and was a recipient of IBM PhD Fellowship in 2004-5. He received SRC Technical Excellence award in 2005, and Best paper awards at IEEE Nano in 2003, International Conference on Computer Design in 2004, and SRC Techcon in 2005.

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Researchers should cite this work as follows:

  • Saibal Mukhopadhyay (2006), "Switching Energy in CMOS Logic: How far are we from physical limit?," http://nanohub.org/resources/1250.

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