Aggressive scaling of CMOS devices in technology generation has resulted in exponential growth in device performance, integration density and computing power. However, the power dissipated by a silicon chip is also increasing in every generation and emerging as a major bottleneck to technology scaling in nanometer technologies. Hence, analysis and reduction of switching energy in binary logic has drawn significant research interest in recent years.
Physical analysis of a binary system shows that, a binary switching can be achieved by dissipating energy as low as kBTln(2). However, International Technology Roadmap for Semiconductor suggests that, a minimum size inverter designed in 45nm node will take approximately 40,000kBT to switch. This talk will discuss the basic principles of CMOS switching from the circuit/system perspective to analyze the above difference between the physical limit of switching energy and its practical value.
Researchers should cite this work as follows:
EE Building, Room 317