As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention from both the semiconductor industry and academia. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this thesis are:
- to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and bandstructure) by performing computer-based simulations, and
- to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. A full three-dimensional, self-consistent, ballistic SNWT simulator has been developed based on the effective-mass approximation with which we have evaluated the upper performance limits of SNWTs with various cross-sections (i.e., triangular, rectangular and cylindrical).
The results show that SNWTs provide better scaling capability than planar MOSFETs. A microscopic, quantum treatment of surface roughness scattering (SRS) in SNWTs has also been accomplished, and it shows that SRS is less important in SNWTs with small diameters than in planar MOSFETs. Finally, bandstructure effects in SNWTs with small diameters have been examined by using an empirical tight binding model, and a channel orientation optimization has been done for both silicon and germanium nanowire field-effect transistors.
PhD thesis for Jing Wang, funded by the Semiconductor Research Corporation (SRC), the MARCO focus center on Materials, Structures and Devices (MSD), and the NSF Network for Computational Nanotechnology (NCN).
Cite this work
Researchers should cite this work as follows:
- Wang, Jing. Ph.D., Purdue University, August, 2005. Device Physics and Simulation of Silicon Nanowire Transistors. Major Professor: Mark S. Lundstrom.