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Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3)

By Souvik Mahapatra

Electrical Engineering, IIT Bombay, India

Published on


This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON gate insulators in order to keep up with Moore's scaling law. The issue is still relevant and also very much exits in the recently introduced HKMG gate stacks.

In part 3, the final part, I will discuss NBTI physical mechanism, and build a simple model to explain measured data obtained from a wide variety of devices during DC stress, recovery following DC stress and during AC stress as a function of frequency and duty cycle. A predictive model for lifetime determination under use condition will also be discussed.

Tags, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.