ECE 595Z Lecture 21: Timing Analysis and Optimization I

By Anand Raghunathan

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

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Researchers should cite this work as follows:

  • Anand Raghunathan (2012), "ECE 595Z Lecture 21: Timing Analysis and Optimization I," http://nanohub.org/resources/15453.

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EE 224, Purdue University, West Lafayette, IN

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ECE 595Z Lecture 21: Timing Analysis and Optimization I
  • Lecture 21: Timing Analysis and Optimization 1. Lecture 21: Timing Analysis an… 0
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  • Technology mapping: Re-cap 2. Technology mapping: Re-cap 20.133333333333333
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  • Technology mapping: Remaining questions 3. Technology mapping: Remaining … 148.3
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  • Technology Mapping for Delay 4. Technology Mapping for Delay 241.2
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  • Technology Mapping for Delay : Constant Delay Model 5. Technology Mapping for Delay :… 487.36666666666667
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  • Technology Mapping for Delay : Load-dependent Delay Model 6. Technology Mapping for Delay :… 729.16666666666663
    00:00/00:00
  • Partitioning a DAG into Trees 7. Partitioning a DAG into Trees 1038
    00:00/00:00
  • Partitioning a DAG into Trees 8. Partitioning a DAG into Trees 1216
    00:00/00:00
  • Summary: Technology Mapping 9. Summary: Technology Mapping 1392.5666666666666
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  • General Principles 10. General Principles 1673.1666666666667
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  • Suggested Reading 11. Suggested Reading 1760.5666666666666
    00:00/00:00
  • Acknowledgments 12. Acknowledgments 1780.1666666666667
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  • ECE 595Z Digital VLSI Design Automation Module 6 (Lectures 21-24): Timing Analysis and Optimization Lecture 21 13. ECE 595Z Digital VLSI Design A… 1788.0333333333333
    00:00/00:00
  • Timing Optimization 14. Timing Optimization 1807.4
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  • Timing Analysis 15. Timing Analysis 1872.1
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  • Outline 16. Outline 1934.9
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  • Timing Analysis 17. Timing Analysis 2035.5333333333333
    00:00/00:00
  • Clocking Criteria for Sequential Circuits 18. Clocking Criteria for Sequenti… 2039.7
    00:00/00:00
  • Setup Condition 19. Setup Condition 2147.9
    00:00/00:00
  • Setup Criterion for Sequential Circuits 20. Setup Criterion for Sequential… 2221.9666666666667
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  • Hold Condition 21. Hold Condition 2515.6333333333332
    00:00/00:00
  • Hold Criterion for Sequential Circuits 22. Hold Criterion for Sequential … 2595.8666666666668
    00:00/00:00
  • Delay Models for Gates 23. Delay Models for Gates 2669.8666666666668
    00:00/00:00
  • Unit Delay Model 24. Unit Delay Model 2783.4333333333334
    00:00/00:00
  • Constant Delay Model 25. Constant Delay Model 2849.8333333333335
    00:00/00:00
  • Pin-to-Pin Delay Model 26. Pin-to-Pin Delay Model 2898.6
    00:00/00:00
  • State / Transition Dependent Delay Model 27. State / Transition Dependent D… 3018.0333333333333
    00:00/00:00
  • Load and Slew Rate Dependent Model 28. Load and Slew Rate Dependent M… 3349
    00:00/00:00
  • PVT Corners 29. PVT Corners 3540.7
    00:00/00:00
  • Summary 30. Summary 3886.5
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