Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented. The promising devices – tunneling FET and spin wave devices – were predicted to perform > 1015 Integer Ops/s/cm2 with power < 1W/cm2.
Birck Nanotechnology Building, Room 1001, Purdue University, West Lafayette, IN