The process of shrinking semiconductor devices employed for fifty years has almost reached its end. Fundamental limitations of the field effect device prevent much additional reduction in the supply voltage. This leads to unavoidable off-state leakage and very high operating power, an intolerable situation, especially for mobile applications. This is leading to radical changes in the roadmap, forecasting separate technologies for high performance, low operating power, and low standby power applications. Scaling will not provide significant performance improvements for the latter two. While research into novel devices is underway, progress has been much slower than one might like.
This talk discusses a rather surprising possibility: the use of carbon-based materials such as carbon nanotubes and grapheneto make nanomechanical switches with at least an order of magnitude lower power dissipation than the low power CMOS options and performance between the various CMOS technologies. It is the unusual properties of these materials that make possible such high performance, very low power digital logic. The technological barriers needed to realize such a technology will be discussed along with work that has been done to demonstrate possible solutions. The potential implications of such a technology will be discussed.
Researchers should cite this work as follows:
Birck Nanotechnology Building, Room 1001, Purdue University, West Lafayette, IN