Naresh Shanbhag, Professor of Electrical and Computer Engineering, University of Illinois
Naresh R. Shanbhag is a Professor in the Department of Electrical and Computer Engineering, and a Research Professor in the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications and signal processing.
Professor Shanbhag received his Ph.D. degree from the University of Minnesota in 1993 in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he was the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. He was a visiting faculty at the National Taiwan University, Taipei, Taiwan, in Fall 2007. Since 1996, Professor Shanbhag is leading the Alternative Computational Models research theme in the DOD and Semiconductor Research Corporation (SRC) sponsored Gigascale Systems Research Center, under the Focus Center Research Program (FCRP).
Researchers should cite this work as follows:
Naresh Shanbhag (2013), "[Illinois] CNST 2013: Computing in the Nanoscale Era," http://nanohub.org/resources/18157.
MNTL, University of Illinois, Urbana-Champaign, Urbana, IL