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Nanoelectronic Architectures

By Greg Snider

Hewlett-Packard Laboratories

Published on

Abstract

Nanoelectronic architectures at this point are necessarily speculative: We are still evaluating many different approaches to fabrication and are exploring unconventional devices made possible at the nano scale. This talk will start off with a review of some "classical" crossbar structures using conventional devices (FETs, diodes, resistors, etc.) and how they might be used for computation. The second half will focus on an unconventional device, the hysteretic resistor, and will present three very different architectures based on it that are capable of computation. Time permitting, I'll also demonstrate some of the compilation and simulation tools we've developed to support our research.

Bio

Greg Snider is currently a consultant to Hewlett-Packard Laboratories where he investigates nanoelectronic architectures, circuits, compilation and simulation. He also consults for Zeidman Technologies, where he is developing synthesis tools for embedded, real-time systems. Past work includes communications, processor design, medical instrumentation, imaging, networking, operating systems, computer security, memory systems, compilers, hardware and software synthesis, e-services, simulation, and programmable hardware. In the early 90's, he was the architect and compiler designer of the Teramac simulation system, a defect-tolerant computer built from hundreds of custom field programmable gate arrays.

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Cite this work

Researchers should cite this work as follows:

  • (2005), "Nanoelectronic Architectures," http://nanohub.org/resources/181.

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Time

Location

EE 317, Purdue University, West Lafayette, IN

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