NEEDS: Nano-Engineered Electronic Device Simulation Node
This resource belongs to the NEEDS: Nano-Engineered Electronic Device Simulation Node group.
Verilog-A is the standard language for compact model development and implementation. This talk provides some background on the rationale for and development of Verilog-A, summarizes the current status of the language, and provides a short introduction and some tips for writing good compact models in Verilog-A. Pointers to more extensive references are also provided.
Researchers should cite this work as follows:
Massachusetts Institute of Technology, Cambridge, MA