Guidelines for Writing NEEDS-certified Verilog-A Compact Models

By Tianshi Wang1, Jaijeet Roychowdhury1

1. Electrical Engineering and Computer Sciences, University of California-Berkeley, Berkeley, CA

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Abstract

This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models. For more about the history of Verilog-A and additional guidelines for writing Verilog-A models, see the presentation by Drs. Geoffrey Coram and Colin McAndrew.

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Cite this work

Researchers should cite this work as follows:

  • Tianshi Wang; Jaijeet Roychowdhury (2013), "Guidelines for Writing NEEDS-certified Verilog-A Compact Models," http://nanohub.org/resources/18621.

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Location

Burton Morgan 121, Purdue University, West Lafayette, IN

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Guidelines for Writing NEEDS-certified Verilog-A Compact Models
  • Guidelines for Writing NEEDS-certified Verilog-A Compact Models 1. Guidelines for Writing NEEDS-c… 0
    00:00/00:00
  • Outline 2. Outline 70.6373039706373
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  • How to put a compact model into a simulator? 3. How to put a compact model int… 110.61061061061062
    00:00/00:00
  • NEEDS-certified Verilog-A 4. NEEDS-certified Verilog-A 233.73373373373374
    00:00/00:00
  • NEEDS-certified Verilog-A 5. NEEDS-certified Verilog-A 354.954954954955
    00:00/00:00
  • Compact Model Example: Capacitor 6. Compact Model Example: Capacit… 581.08108108108115
    00:00/00:00
  • Writing Verilog-A: Example 7. Writing Verilog-A: Example 609.50950950950948
    00:00/00:00
  • Writing Verilog-A: Code 8. Writing Verilog-A: Code 683.68368368368374
    00:00/00:00
  • Writing Verilog-A: Recommendations 9. Writing Verilog-A: Recommendat… 789.45612278945612
    00:00/00:00
  • Writing Verilog-A: Example 10. Writing Verilog-A: Example 927.36069402736075
    00:00/00:00
  • Potential Hazards (an incomplete list) 11. Potential Hazards (an incomple… 956.9235902569236
    00:00/00:00
  • Floating Nodes 12. Floating Nodes 1129.4961628294961
    00:00/00:00
  • Events 13. Events 1148.2482482482483
    00:00/00:00
  • Functions 14. Functions 1201.2345679012346
    00:00/00:00
  • ddt() vs idt() 15. ddt() vs idt() 1240.1401401401402
    00:00/00:00
  • Memory States 16. Memory States 1264.6312979646314
    00:00/00:00
  • Implicit Contribution 17. Implicit Contribution 1333.933933933934
    00:00/00:00
  • Implicit Contribution 18. Implicit Contribution 1429.7630964297632
    00:00/00:00
  • Loops 19. Loops 1561.494828161495
    00:00/00:00
  • log() vs. ln() 20. log() vs. ln() 1666.2996329662997
    00:00/00:00
  • Discontinuity 21. Discontinuity 1691.1244577911245
    00:00/00:00
  • Numerical Hazards 22. Numerical Hazards 1808.8755422088757
    00:00/00:00
  • Summarizing Potential Hazards 23. Summarizing Potential Hazards 1986.3863863863865
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  • References 24. References 1996.1294627961295
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  • Conclusion 25. Conclusion 2009.1091091091091
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