Introduction to Compact Models and Circuit Simulation

By Jaijeet Roychowdhury

Electrical Engineering and Computer Sciences, University of California-Berkeley, Berkeley, CA

Published on

Abstract

With NEEDS introduction by Mark Lundstrom.

This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models. For more about the history of Verilog-A and additional guidelines for writing verily-A models, see the presentation "Verilog-A: Present Status and Guidelines ," by Drs. Geoffrey Coram and Colin McAndrew.

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Cite this work

Researchers should cite this work as follows:

  • Jaijeet Roychowdhury (2013), " Introduction to Compact Models and Circuit Simulation," https://nanohub.org/resources/18678.

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NEEDS-SRC e-workshop

Tags

Introduction to Compact Models and Circuit Simulation
  • NEEDS: Nano Engineered Electronic Device Simulation NEEDS in a nutshell 1. NEEDS: Nano Engineered Electro… 0
    00:00/00:00
  • NEEDS Vision 2. NEEDS Vision 27.894561227894563
    00:00/00:00
  • NEEDS is about compact models… 3. NEEDS is about compact modelsâ… 69.769769769769766
    00:00/00:00
  • two views of compact models… 4. two views of compact models… 144.94494494494495
    00:00/00:00
  • physics to function 5. physics to function 208.04137470804139
    00:00/00:00
  • NEEDS Mission 6. NEEDS Mission 227.59426092759426
    00:00/00:00
  • NEEDS-SPICE: A System for Easing the Development of Simulation-Ready Compact Models 7. NEEDS-SPICE: A System for Easi… 302.70270270270271
    00:00/00:00
  • Today: Many Experimental Devices 8. Today: Many Experimental Devic… 337.2038705372039
    00:00/00:00
  • NEEDS-SPICE and its Goals 9. NEEDS-SPICE and its Goals 537.60427093760427
    00:00/00:00
  • Why Not Just Use Verilog-A? 10. Why Not Just Use Verilog-A? 770.10343677010349
    00:00/00:00
  • Example: Convergence Hooks 11. Example: Convergence Hooks 1025.3920587253922
    00:00/00:00
  • NR: Convergence is Not Guaranteed! 12. NR: Convergence is Not Guarant… 1263.9305972639306
    00:00/00:00
  • Compact Model Development Flows 13. Compact Model Development Flow… 1479.512846179513
    00:00/00:00
  • Verilog-A-based Model Development Flow 14. Verilog-A-based Model Developm… 1499.8998998999
    00:00/00:00
  • NEEDS-SPICE Model Development Flow 15. NEEDS-SPICE Model Development … 2031.3313313313315
    00:00/00:00
  • NEEDS-SPICE Model Development Flow (2) 16. NEEDS-SPICE Model Development … 2367.6009342676011
    00:00/00:00
  • NEEDS-SPICE Model Development Flow (3) 17. NEEDS-SPICE Model Development … 2465.5989322655992
    00:00/00:00
  • Summary and Conclusion 18. Summary and Conclusion 2702.902902902903
    00:00/00:00