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The Limits of CMOS Scaling from a Power-Constrained Technology Optimization Perspective

By David J. Frank

IBM Research Division, Thomas J. Watson Research Center

Published on

Abstract

As CMOS scaling progresses, it is becoming very clear that power dissipation plays a dominant role in limiting how far scaling can go. This talk will briefly describe the various physical effects that arise at the limits of scaling, and will then turn to an analysis of scaling in the presence of power constraints. Since the goal of CMOS technology development is high system performance (not just high device performance), the scaling analysis is carried out in the context of a microprocessor chip. A set of simplified models have been developed to estimate the performance of such a chip on the basis of the underlying technology parameters, such as the doping, the gate length, and the oxide thickness. These models enable fast turnaround comparative technology optimizations in the presence of power and temperature constraints. Using this tool, the dependence of optimal technology parameters on application power requirements has been investigated, as well as the dependence of chip performance on potential technology enhancements. These optimizations also lead to approximate lower bounds on average switching energy, which will be discussed.

Bio

Dr. Frank received his B.S. from the California Institute of Technology, Pasadena, CA in 1977 and a Ph.D. in physics from Harvard University, Cambridge, MA in 1983. Since graduation he has been employed at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, III-V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as power consumption, discrete dopant effects and short-channel effects associated with high-k gate insulators, exploring various nanotechnologies, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low power circuit design. Dr. Frank is an IEEE Fellow and has served as chairman of the Si Nanoelectronics Workshop and is an associate editor of IEEE Transactions on Nanotechnology. He has authored or co-authored 100 technical publications and holds 10 U.S. Patents.

Cite this work

Researchers should cite this work as follows:

  • (2006), "The Limits of CMOS Scaling from a Power-Constrained Technology Optimization Perspective," http://nanohub.org/resources/1883.

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Location

EE Building, Room 117

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