As CMOS scaling progresses, it is becoming very clear that power dissipation plays a dominant role in limiting how far scaling can go. This talk will briefly describe the various physical effects that arise at the limits of scaling, and will then turn to an analysis of scaling in the presence of power constraints. Since the goal of CMOS technology development is high system performance (not just high device performance), the scaling analysis is carried out in the context of a microprocessor chip. A set of simplified models have been developed to estimate the performance of such a chip on the basis of the underlying technology parameters, such as the doping, the gate length, and the oxide thickness. These models enable fast turnaround comparative technology optimizations in the presence of power and temperature constraints. Using this tool, the dependence of optimal technology parameters on application power requirements has been investigated, as well as the dependence of chip performance on potential technology enhancements. These optimizations also lead to approximate lower bounds on average switching energy, which will be discussed.
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EE Building, Room 117