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The Limits of CMOS Scaling from a Power-Constrained Technology Optimization Perspective

By David J. Frank

IBM Research Division, Thomas J. Watson Research Center

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.