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This tarball contains Verilog-A compact lookup table models for 5nm gate length Si FinFETs which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table models was generated using NEMO5 atomistic tight binding transport simulator (also available on Nanohub.org).
There are 3 different device models available depending on the degree of gate underlap. Usage notes, an example 2 input NAND netlist and device descriptions are also included.
* r1.2 - For uniformity, in Dev2_2/, both n and p FinFET models are now for the case with longer underlap on source side. Previously, only n FinFET model had longer underlap on source side and the p FinFET was left to be same as in Dev2_1/
* r1.1 - For the asymmetric underlap device (Dev2), Dev2_1/ contains model data for the case when longer underlap is on drain side and Dev2_2/ contains model data for the case when longer underlap is on source side.
We wish to thank the NEMO5 team for granting us access to the NEMO5 simulator and for providing technical support.
This work was funded under the DARPA PERFECT program.
Tillmann Christoph Kubis; Michael Povolotskyi; Jean Michel D Sellier; James Fonseca; Gerhard Klimeck (2012), "NEMO5 Overview Presentation," https://nanohub.org/resources/14701.
HSPICE - http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx
Verilog-A - http://www.accellera.org/downloads/standards/v-ams/VAMS-LRM-2-3-1.pdf
A. A. Goud, S. K. Gupta, S. H. Choday, and K. Roy, "Atomistic Tight-Binding based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5 nm Gate Length Si FinFETs", Device Research Conference Digest, June 2013.
Researchers should cite this work as follows:
Arun Goud Akkala; Sumeet Kumar Gupta; Sri Harsha Choday; Kaushik Roy (2013), "5nm Si FinFET Models for Circuit Simulations," https://nanohub.org/resources/19195.