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Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in leakage current, increased process parameter variations, and new reliability concerns. Hence, reliable, low-power designs require a shift in design paradigm. We believe that device aware circuit and architecture design along with statistical design techniques can provide large improvement in power dissipation while providing the required reliability and yield. In the two lectures I will present device aware CMOS design to address power, reliability, and process variations in scaled technologies for different application domains — high-performance with power as constraint and ultra-low power with reasonable performance.
Researchers should cite this work as follows:
Kaushik Roy (2006), "Design in the Nanometer Regime: Process Variation," https://nanohub.org/resources/2018.
EE Building, Room 118