Support

Support Options

Submit a Support Ticket

 
HomeResourcesOnline PresentationsDesign of CMOS Circuits in the Nanometer Regime: Leakage Tolerance › Reviews

Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance

By Kaushik Roy

Purdue University

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies.