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You are here: Home › Resources › Online Presentations › Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance › Supporting Docs

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Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance

Purdue University

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See also

Part of: NCN Nanoelectronics: Tutorials
Part of: Nanotechnology 501 Lecture Series

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Supporting Docs

(SWF) Presentation (with audio)
(PDF, 1.58 Mb) Presentation Slides
(MP4, 52.85 Mb) Podcast (video)
(MP3, 30.97 Mb) Podcast (audio)

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