NEEDS: Nano-Engineered Electronic Device Simulation Node
This resource belongs to the NEEDS: Nano-Engineered Electronic Device Simulation Node group.
This talk is directed at device engineers and researchers who need a SPICE-compatible compact model. The assumption is that you understand the physics of the device, you have a set of equations that describe the terminal characteristics, but you’ve never written a compact model before. Some practical advice is provided on how to write a model that is good enough for early stage circuit simulation and that can serve as a starting point for an industrial-strength compact model that circuit designers can use.
Geoffrey is a Staff CAD Engineer at Analog Devices, Inc. (ADI) in Wilmington, MA.
Geoffrey joined ADI in 2000 and works in the CAD development group improving ADI’s internal circuit simulator and evaluating next-generation simulation tools. He has a particular focus on compact device models in Spice simulators.
As part of his efforts in device modeling, Geoffrey chaired the Accellera Verilog-AMS subcommittee for compact modeling extensions. The subcommittee investigated the necessary extensions to Verilog-AMS for it to become the standard, simulator-independent language for Spice modeling and completed its work with the release of Verilog-AMS Language Reference Manual version 2.2 in November of 2004.
Geoffrey received his Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology in 2000, and both his M.E.E. and B.A. from Rice University in 1993.
Researchers should cite this work as follows:
Cory Hall, Rm 540, University of California Berkeley, Berkeley, CA