Writing Your First Verilog-A Compact Model

By Geoffrey Coram

Analog Devices, Inc.

Published on

Abstract

This talk is directed at device engineers and researchers who need a SPICE-compatible compact model. The assumption is that you understand the physics of the device, you have a set of equations that describe the terminal characteristics, but you’ve never written a compact model before. Some practical advice is provided on how to write a model that is good enough for early stage circuit simulation and that can serve as a starting point for an industrial-strength compact model that circuit designers can use.

Bio

Geoffrey is a Staff CAD Engineer at Analog Devices, Inc. (ADI) in Wilmington, MA.

Geoffrey joined ADI in 2000 and works in the CAD development group improving ADI’s internal circuit simulator and evaluating next-generation simulation tools. He has a particular focus on compact device models in Spice simulators.

As part of his efforts in device modeling, Geoffrey chaired the Accellera Verilog-AMS subcommittee for compact modeling extensions. The subcommittee investigated the necessary extensions to Verilog-AMS for it to become the standard, simulator-independent language for Spice modeling and completed its work with the release of Verilog-AMS Language Reference Manual version 2.2 in November of 2004.

Geoffrey received his Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology in 2000, and both his M.E.E. and B.A. from Rice University in 1993.

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Cite this work

Researchers should cite this work as follows:

  • Geoffrey Coram (2014), "Writing Your First Verilog-A Compact Model," http://nanohub.org/resources/20579.

    BibTex | EndNote

Time

Location

Cory Hall, Rm 540, University of California Berkeley, Berkeley, CA

Submitter

NEEDS Node

Purdue University

Writing Your First Verilog-A Compact Model
  • Writing your first Verilog-A compact model 1. Writing your first Verilog-A c… 0
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  • Assumptions 2. Assumptions 98.531865198531875
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  • Question 3. Question 143.81047714381049
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  • Answers 4. Answers 207.24057390724059
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  • Outline 5. Outline 299.79979979979981
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  • 1. Circuit simulators and compact models 6. 1. Circuit simulators and comp… 352.01868535201868
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  • 2. Verilog-A vs. Matlab or C 7. 2. Verilog-A vs. Matlab or C 503.16983650316985
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  • 3. Simple examples 8. 3. Simple examples 634.50116783450119
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  • 3. Simple examples 9. 3. Simple examples 640.90757424090759
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  • 3. Simple examples 10. 3. Simple examples 660.72739406072742
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  • 4. Basic language features 11. 4. Basic language features 697.59759759759766
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  • 4. Basic language features 12. 4. Basic language features 872.93960627293961
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  • 4. Basic language features 13. 4. Basic language features 923.3900567233901
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  • 4. Basic language features 14. 4. Basic language features 1027.6943610276944
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  • 4. Basic language features 15. 4. Basic language features 1117.3506840173507
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  • 3. Simple examples 16. 3. Simple examples 1150.1835168501837
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  • 4. Basic language features 17. 4. Basic language features 1184.2509175842511
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  • 5. Coding guidelines 18. 5. Coding guidelines 1303.2032032032032
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  • 5. Coding guidelines 19. 5. Coding guidelines 1570.8041374708041
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  • 5. Coding guidelines 20. 5. Coding guidelines 1661.5281948615282
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  • 5. Coding guidelines 21. 5. Coding guidelines 1727.8278278278278
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  • 5. Coding guidelines 22. 5. Coding guidelines 1784.0173506840174
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  • 5. Coding guidelines 23. 5. Coding guidelines 1805.6389723056391
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  • 5. Coding guidelines 24. 5. Coding guidelines 1909.7430764097433
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  • 5. Coding guidelines 25. 5. Coding guidelines 1941.5081748415082
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  • 5. Coding guidelines 26. 5. Coding guidelines 2058.8922255588923
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  • 5. Coding guidelines 27. 5. Coding guidelines 2120.7540874207543
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  • 6. Common mistakes 28. 6. Common mistakes 2138.0380380380379
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  • 6. Common mistakes 29. 6. Common mistakes 2219.7197197197197
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  • 6. Common mistakes 30. 6. Common mistakes 2296.5632298965634
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  • 7. Testing your model 31. 7. Testing your model 2355.4554554554556
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  • 7. Testing your model 32. 7. Testing your model 2433.1664998331667
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  • 7. Testing your model 33. 7. Testing your model 2531.9986653319988
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  • 8. The model release package 34. 8. The model release package 2593.7937937937941
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  • 8. The model release package 35. 8. The model release package 2712.2122122122123
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  • 9. Summary 36. 9. Summary 2739.8732065398735
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  • 9. Summary 37. 9. Summary 2792.1921921921921
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  • Further Work 38. Further Work 2858.4584584584586
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  • NEEDS-Basic 39. NEEDS-Basic 3531.6983650316984
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  • Bronze, Silver, Gold 40. Bronze, Silver, Gold 3793.1931931931931
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