Transistor Scaling: The Age of Innovation

By Kaizad Mistry

Intel Corporation, Portland, OR

Published on

Abstract

In the 20th century transistor performance improvement was driven by dimensional scaling; dimensional scaling in turn was driven by scaling of the wavelength of light used for patterning. However, in the last decade, new and innovative techniques have been used to drive transistor performance and dimensional scaling forward. This talk will focus on some of the techniques that have been used to enable Moore’s law over the last decade as well as the prognosis for future scaling

Bio

.Kaizad Mistry Kaizad Mistry is vice president in Intel's Logic Technology Development group. He is currently responsible for directing process development activities for Intel's 10nm logic technology. Most recently, he managed the development of Intel's 22nm logic technology, the world's first to feature 3-D Tri-Gate transistors. Previously, he managed the development of Intel's 45nm logic technology, the world's first to feature high-k plus metal gate transistors. He was the device group manager for Intel's 90nm logic technology and played a leadership role in the world's first implementation of strained silicon transistors. He graduated from the Indian Institute of Technology, Mumbai, in 1984 with a bachelor's degree in electrical engineering and from the University of Southern California, Los Angeles in 1986 with a master's degree in electrical engineering.

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Cite this work

Researchers should cite this work as follows:

  • Kaizad Mistry (2014), "Transistor Scaling: The Age of Innovation," http://nanohub.org/resources/20880.

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Time

Location

Burton Morgan 121, Purdue University, West Lafayette, IN

Submitter

NEEDS Node

Purdue University, West Lafayette, IN