NEEDS: Nano-Engineered Electronic Device Simulation Node
This resource belongs to the NEEDS: Nano-Engineered Electronic Device Simulation Node group.
The III-V Tunnel FET Model is a look-up table based model, where the device current and capacitance characteristics are obtained from calibrated TCAD Sentaurus simulation. Verilog-A models for two types of III-V Tunnel FET, InAs Homojunction Tunnel FET and GaSb-InAs Heterojunction Tunnel, are included.
Model Release Components:
V. Saripalli et al, "Variation-tolerant ultra-low-power heterojunction tunnel FET SRAM design,"IEEE/ACM International Symposium on Nanoscale Architectures, vol. 1, pp. 45-52, Jun. 2011.
R. Bijesh et al, "Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 near broken-gap tunnel FET with ION=740A/μm, GM=700µS/µm and Gigahertz Switching Performance at VDS=0.5V," IEDM Tech. Digest., pp. 28.2.1-28.2.4, Dec. 2013.