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III-V Tunnel FET Model 1.0.0

By Huichu Liu1, Vinay Saripalli1, Vijaykrishnan Narayanan1, Suman Datta1

1. Penn State University

NEEDS: Nano-Engineered Electronic Device Simulation Node

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The III-V Tunnel FET Model is a look-up table based model, where the device current and capacitance characteristics are obtained from calibrated TCAD Sentaurus simulation. Verilog-A models for two types of III-V Tunnel FET, InAs Homojunction Tunnel FET and GaSb-InAs Heterojunction Tunnel, are included.

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Key References

V. Saripalli et al, "Variation-tolerant ultra-low-power heterojunction tunnel FET SRAM design,"IEEE/ACM International Symposium on Nanoscale Architectures, vol. 1, pp. 45-52, Jun. 2011.

R. Bijesh et al, "Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 near broken-gap tunnel FET with ION=740A/μm, GM=700µS/µm and Gigahertz Switching Performance at VDS=0.5V," IEDM Tech. Digest., pp. 28.2.1-28.2.4, Dec. 2013.

Cite this work

Researchers should cite this work as follows:

  • Huichu Liu; Vinay Saripalli; Vijaykrishnan Narayanan; Suman Datta (2014), "III-V Tunnel FET Model 1.0.0,"

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