Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model v. 1.0.0

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Researchers should cite this work as follows:

  • Zizhen Jiang; H.-S. Philip Wong (2014), "Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model v. 1.0.0," http://nanohub.org/resources/21049.

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