VALint: the NEEDS Verilog-A Checker (BETA)

By Xufeng Wang1, Geoffrey Coram2, Colin McAndrew3

1. Purdue University 2. Analog Devices, Inc. 3. Freescale Semiconductor

Verilog-A lint and pretty printer created by NEEDS

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Version 1.0.0 - published on 31 Mar 2017

doi:10.4231/D3HX15S0V cite this

Open source: license | download

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Usage

World usage

Location of all "VALint: the NEEDS Verilog-A Checker (BETA)" Users Since Its Posting

Simulation Users

103

9 20 23 32 36 47 50 55 56 60 63 64 64 67 70 72 74 75 79 81 85 91 92 92 95 100 103

Users By Organization Type
Type Users
Unidentified 63 (61.17%)
Educational - University 34 (33.01%)
Industry 6 (5.83%)
Users by Country of Residence
Country Users
us UNITED STATES 20 (58.82%)
in INDIA 4 (11.76%)
de GERMANY 3 (8.82%)
ru RUSSIAN FEDERATION 1 (2.94%)
bd BANGLADESH 1 (2.94%)
kr KOREA, REPUBLIC OF 1 (2.94%)
tn TUNISIA 1 (2.94%)
br BRAZIL 1 (2.94%)
ve VENEZUELA, BOLIVARIAN REPUBLIC OF 1 (2.94%)
fr FRANCE 1 (2.94%)

Simulation Runs

677

44 146 174 286 312 366 376 404 430 460 470 480 480 486 498 506 510 527 553 567 591 625 633 635 655 671 677
Overview
Average Total
Wall Clock Time 3.51 hours 49.49 days
CPU time 56.86 seconds 5.34 hours
Interaction Time 2.36 hours 33.27 days