Tunnel FET Compact Model

By Hesameddin Ilatikhameneh1; Tarek Ahmed Ameen (editor)1; Fan Chen (editor)1; Ramon Salazar1; Gerhard Klimeck1; Joerg Appenzeller1; Rajib Rahman1

1. Purdue University

Model Tunnel FETs based on analytic modeling and WKB method

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Version 1.0 - published on 24 Aug 2016

doi:10.4231/D36D5PC3P cite this

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World usage

Location of all "Tunnel FET Compact Model" Users Since Its Posting

Cumulative Simulation Users

362

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Simulation Runs

4,607

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Overview
Average Total
Wall Clock Time 2.76 hours 810.36 days
CPU time 13.34 seconds 1.09 days
Interaction Time 12.62 minutes 61.82 days