Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs

By Mark Lundstrom1, Xingshu Sun1, Dimitri Antoniadis2, Shaloo Rakheja2

1. Purdue University 2. Massachusetts Institute of Technology (MIT)

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This presentation is part of the 2015 IEDM short course "Emerging CMOS Technology at 5nm and Beyond".

This Tutorial lecture covers the following topics:

  • IV Theory of Nanotransistors
  • Nanowire FETs
  • Internal Gain MOSFETs
  • Band-to-Band Tunnel FETs
  • 2D channel Materials

This tutorial is part of a larger short course, in which the world's leading experts were invited to give us their vision on what's needed for future CMOS technology to scale to 5 nm and beyond. 5 nm is within a factor of ten of the atomic size, which demands a paradigm shift in many aspects of the technology: device type, process integration, interconnect, patterning, and manufacturability.

For device and material options, III-V MOSFETs, band-to-band tunnel FETs, nanowire FETs, and 2D semiconductors were considered, among other options. Their merits and challenges, with reference to today's state-of-the-art 14 nm FinFETs, will be discussed. For process integration, the focus is on scaling of fully depleted devices, FinFETs, high-mobility channel material, and SRAM cell. Opportunities include horizontal and vertical nanowires with 3D integration. Interconnects will face power dissipation, insufficient bandwidth, and signal latency problems. The question is how far can we push C/low-k to its physical limitation? And will alternative schemes, like carbon nanotubes, optical interconnects, and 3D interconnects meet the challenge? Patterning at 5 nm and beyond will be extremely demanding, requiring a multiplex of resolution enhancing techniques and extreme ultra-violet lithography whose status will be reviewed. Challenges on the resist and mask will also have to be met. Variability is the maker or breaker of CMOS manufacturing at 5 nm. Various sources of local, global, and time dependent variability will be examined. Design-technology co-optimization (DTCO) were discussed as one of the possible solutions. The short course concluded with a few thoughts from the organizer on the historical perspective. 


Mark Lundstrom is the Don and Carol Scifres Distinguished Professor of Electrical and Computer Engineering at Purdue University. He received Ph.D. from Purdue University in 1980 and BEE and MSEE degrees from the University of Minnesota in 1973 and 1974. Between his MSEE and Ph.D. degrees. he worked at Hewlett-Packard Corporation on integrated circuit process development and manufacturing. At Purdue, his research has explored a wide range of semiconductor devices, the physics of carrier transport, and the modeling and numerical simulation of devices. His current focus is on energy conversion devices such as solar cells and thermoelectric devices and on the ultimate transistor. Lundstrom was the founding director of the Network for Computational Nanotechnology and nanoHUB.org, a science gateway that now serves a worldwide nanotechnology community of more that 300,000 individuals. He currently leads NEEDS, an NSF and industry-funded, multi-university initiative focused on newera electronics, and he leads the nanoHUB-U initiative for on-line education. Dr. Lundstrom is a fellow of the Institute of Electrical and Electronic Engineers (IEEE), the American Physical Society, and the American Association for the Advancement of Science (AAAS). He has received several awards for his teaching and research, is a Thompson-Reuters Highly Cited Researcher in Engineering and is a member of the U.S. National Academy of Engineering.

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Researchers should cite this work as follows:

  • Mark Lundstrom, Xingshu Sun, Dimitri Antoniadis, Shaloo Rakheja (2015), "Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs," http://nanohub.org/resources/23273.

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