This presentation is part of the 2015 IEDM short course "Emerging CMOS Technology at 5nm and Beyond"
This Tutorial lecture covers the following topics:
- Extending the Cu/low-k integration
- Cu volume and grain size
- Physical limitation to RC performance
- Electromigration and TDDB reliability
This tutorial is part of a larger short course, in which the world's leading experts were invited to give us their vision on what's needed for future CMOS technology to scale to 5 nm and beyond. 5 nm is within a factor of ten of the atomic size, which demands a paradigm shift in many aspects of the technology: device type, process integration, interconnect, patterning, and manufacturability.
For device and material options, III-V MOSFETs, band-to-band tunnel FETs, nanowire FETs, and 2D semiconductors were considered, among other options. Their merits and challenges, with reference to today's state-of-the-art 14 nm FinFETs, will be discussed. For process integration, the focus is on scaling of fully depleted devices, FinFETs, high-mobility channel material, and SRAM cell. Opportunities include horizontal and vertical nanowires with 3D integration. Interconnects will face power dissipation, insufficient bandwidth, and signal latency problems. The question is how far can we push C/low-k to its physical limitation? And will alternative schemes, like carbon nanotubes, optical interconnects, and 3D interconnects meet the challenge? Patterning at 5 nm and beyond will be extremely demanding, requiring a multiplex of resolution enhancing techniques and extreme ultra-violet lithography whose status will be reviewed. Challenges on the resist and mask will also have to be met. Variability is the maker or breaker of CMOS manufacturing at 5 nm. Various sources of local, global, and time dependent variability will be examined. Design-technology co-optimization (DTCO) were discussed as one of the possible solutions. The short course concluded with a few thoughts from the organizer on the historical perspective.
Takeshi Nogami is a Research Staff member of IBM Research in Albany Nano Tech Center. He received BE, ME, and Ph.D. in chemical engineering from University of Tokyo, Tokyo Japan. He worked for Toshiba Corp., Kawasaki Steel Corp., Advanced Micro Devices Inc., and Sony Corp. prior to joining IBM in 2006. He has been working on copper interconnect technology. His recent work includes the CuMn alloy seed Low-k/Cu integration, CVD-Co liner application to fine dimension BEOL, and various diffusion barrier assessment for 10 nm and beyond. His most recent work which is presented in this IEDM 2015 is a break-through technology to achieve low line/via resistance and high EM reliability simultaneously in 10 nm node and beyond by introduction of a new barrier/liner/seed integration scheme named as through-cobalt selfforming barrier (tCoSFB). He is a holder of 124 U.S. patents.